搜索资源列表
ddr_verilog_xilinx
- DDR（双速率）SDRAM控制器参考设计，xilinx提供-DDR (double data rate) SDRAM controller reference design for Xilinx
DDR_SDRAM_use_in_embedded
- 很多嵌入式系统，特别是应用于图像处理与高速数据采集等场合的嵌入式系统，都需要高速缓存大量的数据。DDR（Double Data Rate，双数据速率）SDRAM由于其速度快、容量大，而且价格便宜，因此能够很好地满足上述场合对大量数据缓存的需求。但DDR SDRAM的接口不能直接与现今的微处理器和DSP的存储器接口相连，需要在其间插入控制器实现微处理器或DSP对存储器的控制。-many embedded systems, especially for image processing and hi
DDR_SDRAM_Controller
- DDR RAM控制器的VHDL源码，实现平台是Lattice FPGA，功能验证通过-DDR RAM controller VHDL source code, achieving the platform of Lattice FPGA, functional verification through
ddr_ctrlv
- ddr ram controller vhdl code
ddr_sdram_controller_vhdl.rar
- DDR SDRAM控制器的VHDL代码已经测试,DDR SDRAM controller VHDL code
DDRSDRAM_controller
- ddr sdram控制器，lattice器件的参考设计，比较详细-ddr sdram controller, lattice components of the reference design, very detailed
sram
- sram操作vhdl源程序，内有sdram模型，控制器设计，及测试源程序-sram operating in vhdl \doc DDR SDRAM reference design documentation \model Contains the vhdl SDRAM model \route Contains the Quartus 2000.05 project files a routed controller design \simulation
DDR2deFPGAsheji
- 使用 Virtex-4 FPGA 器件实现DDR SDRAM控制器以及DDR2 SDRAM操作时序-Using the Virtex-4 FPGA devices to achieve DDR SDRAM and DDR2 SDRAM controller operation timing
DDRSDRAM
- 用vdhl编写的DDR sdram控制器，采用模块化编写，条理清楚，注解详细，附有存储器的说明。-the ddr sdram controller base vhdl
ddr_sdr
- ddr ram控制器，使用vhdl语言实现-ddr ram controller,designed by vhdl
sdram_vhdl
- DDR（双速率）SDRAM控制器参考设计verilog代码，可以直接用的，很好的。-DDR (double rate) SDRAM controller reference design Verilog code, can be directly used, very good.
ug230.pdf
- The Spartan-3E Starter Kit board highlights the unique features of the Spartan-3E FPGA family and provides a convenient development board for embedded processing applications. The board highlights these features: • Spartan-3E FPGA specific fe
ddr_sdr_latest[1].tar
- ddr sdram 控制器的接口，为工业标准化存储设备提供简单的接口-The DDR SDRAM Controller provides the user with a simplified interface to industry standard memory devices. Using this controller makes accesses to DDR SDRAM devices as simple as possible.
ug_ddr_sdram
- DDR and DDR2 SDRAM Controller Compiler 的用户向导-DDR and DDR2 SDRAM Controller Compiler User Guide
DDDRR_SDRAM_cD
- DDR SRAM控制器的verilog完整设设计文档（包含有完整的verilog源代码）， -DDR SRAM controller the verilog complete set design document (contains the complete source code verilog)
DDRSDRAM
- 基于VHDL的DDR SDRAM控制器的设计，实现数据的读写功能，迸发长度分为2，4，8-Based on the VHDL DDR SDRAM controller design, implementation of data read and write capabilities, burst into the length of 2, 4, 8
dab1814114c3
- 此為採用ALTERA所做的DDR 控制器(verilog)- File/Directory Descr iption ============================================================================= \doc DDR SDRAM reference design documentation \model Contains the verilog SDRAM model \route
ddr3_top
- xilinx DDR verilog 控制器-DDR verilog controller FOR XILINX
Chapter-9
- 9.1 异步FIFO设计实例 9.2 DDR SDRAM Controller设计实例-9.1 Asynchronous FIFO design example 9.2 DDR SDRAM Controller Design Example
ddr_sdram
- this document explain de function of ddr sdram controller